1. Technical Field
The present invention relates to a method and system for improving data processing in general, and in particular, to an improved method and system for executing instructions within a processor. Still more particularly, the present invention relates to an improved method and system for executing context-altering instructions within a processor without context synchronization.
2. Description of the Related Art
A "context" is the environment (e.g. privilege or relocation) in which a program executes and it is generally controlled by the content of certain system register (e.g. machine state register) within a processor. Context-altering instructions are a class of instructions that change the context of the processor in which data addresses or instruction addresses are interpreted, or in which instructions are executed. They include system calls, traps, return-from-interrupt, etc. Such instructions can be very useful because they allow an application program to request services from the operating system by means of system call or conditional trap; and after completion of these services or after time-sliced out, the control is returned back to the application program via return-from-interrupt.
However, the processor time overhead for executing context-altering instructions is also very high because a context synchronization must be preformed after each execution of context-altering instructions. The context synchronization operation allows any instruction that follows to be fetched and executed in the context established by the operation. This requirement dictates that any pre-fetched instruction be discarded, which in turn requires that any result of speculative execution also be discarded. Further, the serialized fashion of instruction execution does not take advantage of the pipelined architecture of the processor and incidentally poses a huge time penalty for executing context-altering instructions. A superscalar pipelined processor achieves its high instruction throughput by fetching and dispatching multiple instructions in a single machine cycle, and typically fetches instructions ahead of the instructions currently being executed in order to avoid delay. However, as a result of a context synchronization operation after the execution of a context-altering instruction, all the pre-fetched instructions subsequent to the context-altering instruction must be discarded and need to be re-fetched. This problem can be better illustrated with a diagram. FIG. 3a is an illustration of a three level pipeline. Instr.sub.-- 1 is a context-altering instruction and the context of the processor is changed from "1" to "0" at the completion cycle of Instr.sub.-- 1 in cycle 3. If the instructions subsequent to Instr.sub.-- 1, such as Instr.sub.-- 2, Instr.sub.-- 3, etc., cannot be run in context "0", they will all have to be discarded during the context synchronization and need to be re-fetched for decoding under context "0". This problem is even more prominent in processors that utilize parallel pipelines because many more pre-fetched instructions will be discarded.
Consequently, it would be desirable to provide a method for executing these context-altering instructions efficiently by avoiding subsequent delays in machine cycle time due to unnecessary discarding of pre-fetched instructions.